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rev. 4149m?aero?06/04 1 features 8032 pin and instruction compatible four 8-bit i/o ports three 16-bit timer/counters 256 bytes ram full-duplex uart asynchronous port reset 6 sources, 2 level interrupt structure 64 kbytes program memory space 64 kbytes data memory space power control modes idle mode power-down mode on-chip oscillator operating frequency: 30 mhz power supply: 4.5v to 5.5v temperature range: military (-55 o c to 125 o c) no single event latch-up below a let threshold of 80 mev/mg/cm 2 tested up to a total dose of 30 krads (si) according to mil std 883 method 1019 packages: side brazed 40-pin, mqfpj 44-pin qml q and v with smd 5962-00518 scc c an b with specification scc9521002 description the 80c32e is a radiation tolerant romless version of the 80c52 single chip 8-bit microcontroller. the 80c32e retains all the features of the 80c32 with 256 bytes of internal ram, a 6- source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters. the fully static design of the 80c32e reduces system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. the 80c32e has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the timers, the serial port and the interrupt system are still operating. in the power-down mode the ram is saved and all other functions are inoperative. rad. tolerant 8-bit romless microcontroller 80c32e
2 80c32e 4149m?aero?06/04 block diagram pin configuration note: nic: no internal connection timer 0 int ram 256x8 t0 t1 rxd txd wr rd ea psen ale xtal2 xtal1 uart cpu int1 ctrl int0 c51 core port 0 p0 port 1 port 2 port 3 parallel i/o ports & ext. bus p1 p2 p3 ib-bus rst timer 1 timer 2 t2 t2ex 5 4 3 2 1 6 44 43 42 41 40 p1.4 p1.0 p1.1 p1.3 p1.2 nic* vcc p0.0/ad0 p0.2/ad2 p0.1/ad1 p0.4/ad4 p0.6/ad6 p0.5/ad5 p0.7/ad7 ale psen ea nic* p2.7/a15 p2.5/a13 p2.6/a14 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p1.5 p1.6 p1.7 rst p3.0/rxd nic* p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p0.3/ad3 nic* 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 mqfpj44 18 19 20 21 22 23 24 25 26 27 28 p1.7 rst p3.0/rxd p3.1/txd p1.3 1 p1.5 p3.2/int0 p3.3/int1 p3.5/t1 p3.6/wr p3.7/rd xtal2 xtal1 vss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p0.4/a4 p0.6/a6 p0.5/a5 p0.7/a7 ale psen ea/vpp p2.7/a15 p2.5/a13 p2.6/a14 p1.0/t2 p1.1/t2ex vcc p0.0/a0 p0.1/a1 p0.2/a2 p0.3/a3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 sb40 p1.6 p1.4 p1.2 p3.4/t0
3 80c32e 4149m?aero?06/04 pin description mnemonic type name and function v ss i ground: 0v reference v cc i power supply: this is the power supply voltage for normal, idle and power-down operation p0.0-p0.7 i/o port 0 : port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. port 0 pins must be polarized to vcc or vss in order to prevent any parasitic current consumption. port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. in this application, it uses strong internal pull-up when emitting 1s. p1.0-p1.7 i/o port 1 : port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. p2.0-p2.7 i/o port 2 : port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally pulled low will source current because of the internal pull-ups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr).in this application, it uses strong internal pull-ups emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 emits the contents of the p2 sfr. p3.0-p3.7 i/o port 3 : port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. port 3 also serves the special features of the 80c51 family, as listed below. i rxd (p3.0): serial input port o txd (p3.1): serial output port i int0 (p3.2): external interrupt 0 i int1 (p3.3): external interrupt 1 i t0 (p3.4): timer 0 external input i t1 (p3.5): timer 1 external input o wr (p3.6): external data memory write strobe o rd (p3.7): external data memory read strobe rst i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc.
4 80c32e 4149m?aero?06/04 ale o (i) address latch enable: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. psen o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea i external access enable: ea must be externally held low to enable the device to fetch code from external program memory locations. xtal1 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 o crystal 2: output from the inverting oscillator amplifier mnemonic type name and function
5 80c32e 4149m?aero?06/04 idle and power-down operation idle mode allows the interrupt, serial port and timer blocks to continue to operate while the clock of the cpu is gated off. power-down mode stops the oscillator. table 1. pcon register pcon ? power control register reset value = 000x 0000 not bit addressable 76543210 smod - - - gf1 gf0 pd idl bit number bit mnemonic description 7smod double baud rate bit set to select double baud rate in mode 1, 2 or 3. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3gf1 general-purpose flag cleared by user for general-purpose usage. set by user for general-purpose usage. 2gf0 general-purpose flag cleared by user for general-purpose usage. set by user for general-purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
6 80c32e 4149m?aero?06/04 idle mode an instruction that sets pcon.0 causes that to be the last instruction executed before going into idle mode. in idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high levels. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminat ing the idle mode. the interrupt will be ser- viced, and following reti the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occurred dur- ing normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. power-down mode to save maximum power, a power-down mode can be invoked by software. in power-down mode, the oscillator is stopped and the instruction that invoked power- down mode is the last instruction executed. the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power- down. to properly terminate power-down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. only external interrupts int0 and int1 are useful to exit from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in figure 1. when both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power-down exit will be completed when the first input will be released. in this case the higher priority interrupt service routine is executed once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put 80c32e into power-down mode. figure 1. power-down exit waveform exit from power-down by reset redefines all the sfrs, exit from power-down by external interrupt does no affect the sfrs. int1 int0 xtal1 power-down phase oscillator restart phase active phase active phase
7 80c32e 4149m?aero?06/04 exit from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. table 2. state of ports during idle and power-down modes mode program memory ale psen port0 port1 port2 port3 idle external 1 1 floating port data address port data power- down external 0 0 floating port data port data port data
8 80c32e 4149m?aero?06/04 hardware description refer to the c51 8-bit microcontroller hardware description manual for details on 80c32e functionality. electrical characteristics absolute maximum ratings (2) ambient temperature under bias. m = military-55 c to 125 c storage temperature .................................... -65 c to + 150 c voltage on v cc to v ss ..........................................-0.5v to + 7v voltage on any pin to v ss ..........................-0.5v to v cc + 0.5v power dissipation ........................................................... 1 w (2) notes: 1. stresses at or above those listed under ? absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. 2. this value is based on the maximum allowable die temperature and the thermal resistance of the package.
9 80c32e 4149m?aero?06/04 dc parameters notes: 1. i cc under reset is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 6), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; ea = rst = port 0 = v cc . i cc would be slightly higher if a crystal oscillator is used. 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c; port 0 = v cc ; ea = rst = v ss (see figure 4). 3. power-down i cc is measured with all output pins disconnected; ea = v ss , port 0 = v cc ; xtal2 nc.; rst = v ss (see fig- ure 5). 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacitive loading 100 pf), the noise pulse on the ale line may exceed 0.45v with maxi v ol peak 0.6v. the use of a schmitt trigger is not necessary. 5. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total i ol for all output pins: 71 ma table 3. dc parameters in standard voltaget a = -55 c to +125 c; v ss = 0v; v cc = 5v 10%; f = 0 to 30 mhz. symbol parameter min. max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 1.4 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3 (5) 0.45 v i ol = 1.6 ma (4) v ol1 output low voltage, port 0, ale, psen (5) 0.45 v i ol = 3.2 ma (4) v oh output high voltage, ports 1, 2, 3 2.4 0.75 v cc 0.9 v cc v v v i oh = -60 a i oh = -25 a i oh = -10 a v oh1 output high voltage, port 0, ale, psen 2.4 0.75 v cc 0.9 v cc v v v i oh = -400 a i oh = -150 a i oh = -40 a r rst rst pull-down resistor 50 200 k ? i il logical 0 input current ports 1, 2 and 3 -75 a vin = 0.45v i li input leakage current 10 a 0.45 v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3 -750 a vin = 2.0v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power-down current (3) 75 a2.0v < v cc < 5.5v i cc power supply current (1)(2)(6) freq = 1 mhz icc op freq = 1 mhz icc idle freq = 6 mhz icc op freq = 6 mhz icc idle freq >12 mhz icc op freq >12 mhz icc idle 1.8 1 10 4 1.25f + 5 0.36f + 2.7 ma ma ma ma ma ma v cc = 5.5v f in mhz
10 80c32e 4149m?aero?06/04 if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 6. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; ea = port 0 = v cc ; rst = v ss . the internal rom runs the code 80 fe (label: sjmp label). i cc would be slightly higher if a crystal oscillator is used. measurements are made with otp products when possible, which is the worst case. figure 2. i cc test condition, under reset figure 3. operating i cc test condition figure 4. i cc test condition, idle mode ea v cc v cc i cc (nc) clock signal v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0 ea v cc v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0 reset = vss after a high pulse during at least 24 clock cycles rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. clock signal reset = vss after a high pulse during at least 24 clock cycles
11 80c32e 4149m?aero?06/04 figure 5. i cc test condition, power-down mode figure 6. clock signal waveform for i cc tests in active and idle modes rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. reset = vss after a high pulse during at least 24 clock cycles v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns.
12 80c32e 4149m?aero?06/04 ac parameters each timing symbol has 5 characters. the first character is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t a = -55 c to +125 c (military temperature range); v ss = 0v; v cc = 5v 10%; load capacitance for port 0, ale and psen = 100 pf; load capacitance for all other outputs = 80 pf. table 4. external program memory characteristics (ns) figure 7. external program memory read cycle symbol parameter 30 mhz min max t lhll ale pulse width 60 t av ll address valid to ale 15 t llax address hold after ale 35 t lliv ale to valid instruction in 100 t llpl ale to psen 25 t plph psen pulse width 80 t pliv psen to valid instruction in 65 t pxix input instruction hold after psen 0 t pxiz input instruction float after psen 30 t pxav psen to address valid 35 t av iv address to valid instruction in 130 t plaz psen low to address float 6 t pliv tplaz ale psen port 0 port 2 a0-a7 a0-a7 instr in instr in instr in address or sfr-p2 address a8-a15 address a8-a15 12 t clcl t av iv t lhll t avll t lliv t llpl t plph t pxav t pxix t pxiz t llax
13 80c32e 4149m?aero?06/04 table 5. external data memory characteristics (ns) figure 8. external data memory write cycle symbol parameter 30 mhz min max t rlrh rd pulse width 180 t wlwh wr pulse width 180 t rldv rd to valid data in 135 t rhdx data hold after rd 0 t rhdz data float after rd 70 t lldv ale to valid data in 235 t av dv address to valid data in 260 t llwl ale to wr or rd 90 115 t av wl address to wr or rd 115 t qvwx data valid to wr transition 20 t qvwh data set-up to wr high 215 t whqx data hold after wr 20 t rlaz rd low to address float 0 t whlh rd or wr high to ale high 20 40 ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t avdv t llax t rldv
14 80c32e 4149m?aero?06/04 figure 9. external data memory read cycle table 6. serial port timing ? shift register mode (ns) figure 10. shift register timing waveforms t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avwl t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh symbol parameter 30 mhz min max t xlxl serial port clock cycle time 400 t qvhx output data set-up to clock rising edge 300 t xhqx output data hold after clock rising edge 50 t xhdx input data hold after clock rising edge 0 t xhdv clock rising edge to input data valid 300 valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid valid valid valid valid valid input data valid
15 80c32e 4149m?aero?06/04 table 7. external clock drive characteristics (xtal1) figure 11. external clock drive waveforms figure 12. ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ?1? and 0.45v for a logic ?0?. timing measurement are made at v ih min for a logic ?1? and v il max for a logic ?0?. figure 13. float waveforms for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20 ma. symbol parameter min max unit t clcl oscillator period 33.33 ns t chcx high time 5ns t clcx low time 5ns t clch rise time 5ns t chcl fall time 5ns v cc -0.5 v 0.45 v 0.7v cc 0.2v cc -0.1v t chcl t clcx t clcl t clch t chcx 0.45v v cc -0.5v 0.2v cc +0.9 0.2v cc -0.1 input/output v ol +0.1v v oh -0.1v float v load v load +0.1v v load -0.1v
16 80c32e 4149m?aero?06/04 figure 14. clock waveforms this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propaga- tion also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. clock xtal2 ale internal state4 state5 state6 state1 state2 state3 state4 state5 external program memory fetch read cycle write cycle serial port shift clock port operation psen p0 p2 (ext) rd p0 p2 p0 p2 wr txd (mode 0) rxd sampled rxd sampled p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled mov dest port (p1, p2, (includes int0, int1, to, t1) mov dest p0 old data new data dpl or rt out data out pcl out (even if memory is internal) pcl out (if program memory is external) indicates dph or p2 sfr to pch transition dpl or rt out float pcl out (if program memory is external) indicates dph or p2 sfr to pch transition indicates address transitions float float float pcl out pcl out pcl out data sampled data sampled data sampled these signals are not activated during the execution of a movx instruction p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 p1p2
17 80c32e 4149m?aero?06/04 ordering information note: 1. please contact atmel for availability. table 8. possible order entries part number speed (mhz) temperature range package quality flow mc-80c32e-30-e 30 25c side brazed 40-pin (.6) engineering samples mj-80c32e-30-e 30 25c mqfpj 44-pin engineering samples mc-80c32e-30 30 -55c to +125c side brazed 40 pin (.6) standard mil. mj-80c32e-30 30 -55c to +125c mqfpj 44-pin standard mil. 5962-0051801qqc 30 -55c to +125c side brazed 40 pin (.6) qml-q 5962-0051801qxc 30 -55c to +125c mqfpj 44-pin qml-q 5962-0051801vqc 30 -55c to +125c side brazed 40 pin (.6) qml-v 5962-0051801vxc 30 -55c to +125c mqfpj 44-pin qml-v scc9521002-01b 30 -55c to +125c side brazed 40 pin (.6) scc b scc9521002-02b 30 -55c to +125c mqfpj 44-pin scc b MM0-80C32E-30-E (1) 30 -55c to +125c die engineering samples 5962-0051801q9a (1) 30 -55c to +125c die qml-q 5962-0051801v9a (1) 30 -55c to +125c die qml-v
18 80c32e 4149m?aero?06/04 package drawings 40-pin side braze (600 mils)
19 80c32e 4149m?aero?06/04 44-pin multilayer quad flat pack
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